ASIC-PD methodology team is hiring senior tool development engineer, who will focus on final timing closure part of an internal tool at the beginning. The role needs both senior STA/timing fixing experience and good software skill (C++, python). The tool is our team's core internal tool which can cover both netlist and physical design related tasks.
What You’ll Be Doing:
Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization
As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.
What We Need To See:
BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience
Minimum 3+ years of relevant experience in CAD software and VLSI hardware design
Strength in both CAD software and VLSI design
Understanding of VLSI timing optimization and related concepts, including timing constraints, corners, power, etc.
Demonstrated ability in software development using C++
Familiarity with design implementation tools such as PrimeTime, Tempus, ICC2, Innovus, and typical design flows written in Perl, Tcl, and Python.
Strong communication and interpersonal skills
Ways To Stand Out From The Crowd:
C++14 or newer experience, such as lambdas and concurrency
Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.
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Last updated: 23 hours ago
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