NVIDIA Clocks and Resets group is looking for a top ASIC engineer with extensive experience in high-speed logic design and gate-level design implementation and optimization! The complexity of clocking structure has grown significantly over years with increased focus on performance and power. Modern clocking designs need to balance high frequency clocks with power optimizations, DFT, crosstalk, routing and other physical implementation and timing closure constraints. We need a dedicated and motivated engineer to work on next generation Clocking implementation for Tegra SOCs.
What you'll be doing:
Micro-architect and Design new clocks modules and topologies in order to support all IPs constituting the SOC.
Understand and evaluate the trade-offs across DFX, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with multiple other SOC functions for SOC Clocking Implementation.
Working on automation and methodology aspects to generate Clocking RTL in most efficient and scalable way.
Get involved in end-to-end cycle of SOC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup!
Get exposure to CDC, RDC, Lint, Synthesis, multi-power-domain designs and latest methodologies.
What we need to see:
B.Tech or M.Tech in Electronics/VLSI or equivalent experience, with 6+ years of relevant industry work experience
Experience in RTL design (Verilog), Gate-level Design and Synthesis
Strong coding skills in Perl or other industry-standard scripting languages
Excellent interpersonal skills and ability to work with multiple teams to brainstorm optimally.
Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a bonus. Prior experience in implementing on-chip clocking networks is a plus.
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Last updated: 23 hours ago
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